In ECL BICMOS circuits, voltage translation circuitry is employed to translate ECL level voltages to CMOS level voltages. A conventional ECL level to CMOS level translation circuit is shown in FIG. 1. In the FIG. 1 circuit, PMOS field-effect transistors PM1 and PM2 function as a voltage gain stage, and NMOS field-effect transistors NM1 and NM2 function as a resistive loading stage for the voltage gain stage.
Throughout the specification, PMOS field-effect transistors will be referred to as "PMOS" transistors, and NMOS field-effect transistors will be referred to as "NMOS" transistors.
Normally, the difference (V.sub.in.sup.+ -V.sub.in.sup.-)=U between the input voltages V.sub.in.sup.+ and V.sub.in.sup.- asserted, respectively, at the gates of transistors PM1 and PM2, is substantially equal to +1 volt or -1 volt. In response to the input voltages V.sub.in.sup.+ and V.sub.in.sup.-, and an appropriate voltage V.sub.cc, the FIG. 1 circuit can develop a CMOS level output voltage V.sub.out, across output capacitor C.sub.out, having magnitude in the range from about 0 volts to about +5 volts.
However, the CMOS voltage translator of FIG. 1 is very slow, particularly under conditions of high temperature and high output loading. This slowness is mainly due to the slow frequency response of the PMOS transistors at high temperature.